• ESD and Latch-up Overview

ESD sensitivity testing was established for the purpose of testing and classifying microcircuits according to their susceptibility to damage or degradation from exposure to electrostatic discharge. The objective is to provide reliable and repeatable test results, so accurate classifications may be performed. This classification is used to specify appropriate packaging and handling requirements, from design through post-production phases.

Latch-up is a failure mechanism of CMOS integrated circuits characterized by excessive current drain coupled with functional failure, parametric failure and/or device destruction. It may be a temporary condition that terminates upon removal of the exciting stimulus, a catastrophic condition that requires the shutdown of the system to clear, or a fatal condition that requires replacement of damaged parts. Regardless of the severity of the condition - latch-up is an undesirable, but controllable phenomenon. In many cases latch-up is avoidable.