Human Body Model (HBM)-
The HBM module simulates the direct transfer of electrostatic charge, from the human body, to a test device. A 100pF capacitor is discharged through a switching component and a 1.5 Kohm series resistor. This is currently the most requested industry model, for classifying device sensitivity to ESD.

JEDEC EIA/JESD22, Method A114-B (JEDEC standard)
MIL-STD-883E, Method 3015.7 (Department of Defense Test Method Standard)
AEC-Q100-002-REV-C (Automotive Electronics Council)
ESD STM 5.1-1998 (ESD Association Standard Test Method)

Machine Model (MM)-
The machine model module emulates the rapid direct transfer of electrostatic charge, from a charged conductive object, such as a metallic tool or fixture, to a test device. This model consists of a discharged 200pF capacitor, with no series resistor. The demand for MM ESD testing has increased, with the replacement of individual packaging by automated systems.

JEDEC EIA/JESD22, Method A115-A (JEDEC standard)
AEC-Q100-003-REV-C (Automotive Electronics Council)
ESD STM 5.2-1999 (ESD Association Standard Test Method)

Charge Device Model (CDM)-
During standard packaging, assembly, and automated processing, integrated circuits may be exposed to rapid electrostatic charge transfer. Triboelectric and electrostatic induction processes lead to component charging. Typical device triboelectrification, occurs during frictional sliding and then rapid discharge, via contact with a conductive object. Laboratory simulated CDM testing is used to classify integrated circuits according to their triboelectric susceptibility. During CDM testing, the device under test is rapidly charged and discharged, through a ground plane. The high-speed discharging and charging pulses are opposite in polarity and approximately equal in magnitude.

JEDEC EIA/JESD22, Method C101-A (JEDEC standard)
ESD STM 5.3.1-1999 (ESD Association Standard Test Method)

Latch-up Testing-
Latch-up testing is performed to determine the device latch-up susceptibility. It is based on the JEDEC specification #17 at the customer’s specified current levels (+200mA), temperature up to 150oC, and configurations (separate VDD’s). Procedures recommended by the JEDEC JC-40.2 CMOS Logic Standardization Committee are followed.

JEDEC EIA/JESD78