Backside sample preparation also referred to as selected area polishing, is a backside grinding and polishing method developed to aid the test and failure analysis of semiconductor devices. Selected area polishing (SAP) is a new term to describe backside grinding in which only part of the package is thinned (i.e. producing a window), so preserving wiring external to the die. The term also refers to the thinning of single dice (or small groups of dies) on the backside of wafers and specific areas on multi-chip modules. The method provides an optimized sample for analysis by photon and thermal emission microscopy as well as infrared microscopy.

Advanced integrated circuit processing and packaging has resulted in blocking access to the active circuitry from the frontside of the die. This has occurred because of
Increase in metal interconnect layers, chemical-mechanical polishing (CMP), and flip-chip designs. These barriers make most frontside analysis tools ineffective.

SAP is required to fully prepare an electrically intact device thinned to 100microns or less with controlled accuracy, no damage, and with a highly polished surface. Thinning and polishing of the die allows Near Infrared (NIR) light to penetrate the backside so that imaging of the circuitry can be done. It also allows the transmission of emission sites to be seen when viewed under an emission microscope (PEM) or other backside tools.